So-called chip film processes for producing thin chips are known from the prior art. Said chip film processes are described, for example, in M. Zimmermann et al., “A Seamless Ultra-Thin Chip Fabrication and Assembly Technology”, Tech. Dig. IEDM, pp. 1010-1012, 2006. In the case of the chip film technology, depressions, which are also designated as “cavities”, are produced on a starting substrate, in particular a carrier wafer composed of conventional silicon, by means of specific etching methods. Said depressions or cavities are produced by producing porous silicon and subsequently removing porous silicon (APSM process). Silicon suitable for circuits is then applied on said cavities by means of an epitaxy method. This applied layer later forms the ultra-thin microchip. The desired circuit structure is then processed on this surface by conventional methods. Afterward, by means of a process also designated as “pick, crack and place” technology, the chip can be sucked up (pick) by a vacuum pipette, detached (crack) from the starting substrate and then positioned (place) on an arbitrary further carrier substrate.
The prior art likewise discloses methods for producing electrical contacts on or through a wafer or chip. By way of example, in this case it is possible to produce narrow holes having virtually perpendicular walls in a wafer, to insulate them and then to fill them wholly or partly with a conductive material, for example metal or silicon. Furthermore, eutectic bonding methods at the wafer level and for so-called “chip-to-wafer processes” are known from microsystems technology. In the area of the applications, approaches for integrating sensor chips and evaluation ICs in a chip composite assembly are known.